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MC9S12XDT256CAG mcu reverse

时间:2016-05-25 13:46:26 click:nums

16-bit HCS12X CPU
Upward compatible with HCS12 instruction set
Interrupt stacking and programmer's model identical to HCS12
Instruction queue
Enhanced indexed addressing
Enhanced instruction set
EBI (external bus interface)
MMC (module mapping control)
INT (interrupt controller)
DBG (debug module to monitor HCS12X CPU and XGATE bus activity)
BDM (background debug mode)
Peripheral coprocessor
Parallel processing module offloads the CPU by providing high-speed data processing transfer between peripheral modules, RAM and I/O ports
Data transfer between flash EEPROM, peripheral modules and I/O ports
Enhanced MSCAN module delivers full CAN performance with virtually unlimited number of mailboxes when used with XGATE
Phase-lock loop (PLL) circuit allows power consumption and performance to be adjusted to suit operational requirements; system power consumption can be further improved with "fast exit from stop mode" feature
I/O ports available in each module and up to 25 additional I/O ports are available with interrupt capability allowing wake-up from stop or wait mode

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